I. Field of the Disclosure
The technology of the disclosure relates generally to memory systems.
II. Background
Computing systems rely on memory for both storage and operation. One common type of memory that computing systems use for operation is random access memory (RAM). RAM has two distinct types—static RAM (SRAM) and dynamic RAM (DRAM). DRAM relies on the presence or absence of a charge on a capacitor in a memory array to indicate a bit value. For example, if the capacitor is charged, the bit value is considered to be a logical one (1). If the capacitor is not charged, the bit value is considered to be a logical zero (0). Because capacitors slowly lose charge, a periodic refresh is applied. When power is terminated, all capacitors discharge, and the memory loses whatever data was present in the DRAM.
Variations in manufacturing processes may result in variations that produce imperfect DRAM, in that not every element in a DRAM module may work as intended. However, when provided knowledge regarding such variations, computing systems may readily compensate for the variations. For example, a computing system may generate greater or lesser voltages to charge the capacitors, may provide compensation for latency, or may even avoid any attempts to write to or read from a completely defective bit cell. Before the computing system may take such remedial steps, though, the computing system needs to determine which DRAM memory array elements (e.g., an individual bit cell) are operational, and what idiosyncrasies may be associated with a particular DRAM memory array element and/or with pathways for communicating with the DRAM memory array elements. Accordingly, the computing system may carry out training operations to optimize a link to a DRAM memory array element for timing and performance, as non-limiting examples.
Conventional training methods rely on serial testing of DRAM memory array elements. For example, in conventional write testing, a write command to a DRAM memory array element is initiated, data is written to the DRAM memory array element, and the data is then read from the DRAM memory array element. A training state machine (or software) may then compare the write data to the read data, and determine whether to modify (e.g., increment or decrement) the parameter that is being trained. While effective, this process may require substantial boot memory to implement, and may be time-consuming due to the DRAM memory access write command and read command that must be issued before a comparison may be made. Moreover, the comparison step may be iterated many times before a final optimal value may be determined. Thus, an improved technique to train memory may be desirable.